Proper operation of a memory array requires that a currently selected wordline be fully deselected (pulling the voltage on the deselected wordline to a LOW) before the selection of a subsequently addressed wordline is made. Consequently, the less time it takes to deselect a previously accessed wordline, the faster the selection of the newly addressed wordline can be accomplished. If more than one wordline is in a selected state at any given time, the content of the data bus will be written into more than one location during the write operation. During the read operation, selection of more than one wordline will allow all the selected addresses to unload their contents, leading to erroneous results on the data bus, and rendering the memory device ineffective and useless.
Semiconductor memory chips generally have a relatively large number of memory cells which are organized into arrays of rows and columns. To select a particular cell in the array, an address which identifies both the column and the row to which the cell is connected must first be decoded.
In a memory array, all of the memory cells in a given row are connected to a single wordline which is pulled HIGH when one of the cells on that row is accessed and is pulled LOW when the access is terminated. The resulting RC load of the wordlines can significantly limit the performance of the memory by increasing the amount of time required to charge and discharge the wordlines during the selection and the deselection phase. Similarly, all the memory cells along a column are connected to the same pair of bitlines.
For many memory arrays, the time required for the deselection of a wordline is a major component of the delay contributing to the memory access time. Therefore, for these memory arrays, the faster a wordline can be pulled down to the deselected voltage level, the sooner another wordline can be selected so that valid data can be written to or read from the addressed cells. For certain applications, such as a cache memory on a microprocessor chip, very fast access times are a necessity in order for the system to take advantage of the high speed of the microprocessor. This makes it even more critical to have a memory circuit that deselects a wordline with a minimum amount of delay.
A row select circuit typically includes a decoder circuit and a driver circuit for each row (wordline) in the memory array. An array with 2.sup.N rows requires an address input of N bits to select a row. Each decoder receives and decodes the N-bit address and in response thereto selects a particular row in the array. The driver circuit of the selected row drives the selected row (wordline), thus allowing a memory cell or cells on the selected row to be accessed (read from or written into). Before this occurs, all of the other rows in the array must be deselected.
Two basic types of wordline drivers have been used to drive the wordlines in a memory array. The first type is the three transistor wordline driver 100 shown in FIG. 1, which contains three MOS transistors 102, 104 and 106. A HIGH voltage on the RLB line (which is the inverse of the voltage on the RL line), turns on the n-channel transistor 106 and pulls the wordline to LOW (V.sub.SS). When the voltage on line RL is HIGH, the wordline will either be pulled HIGH by p-channel transistor 102 if the voltage at node F is LOW, or it will be pulled LOW by n-channel transistor 104 if the voltage at node F is HIGH.
The disadvantages of the three transistor wordline driver are:
1. It is difficult to put three transistors on pitch with smaller wordline widths and spacings. PA1 2. Too many interconnects are required. (The RL and RLB lines need to be run in every wordline driver.) PA1 3. Because of the large time-constant (RC) of the wordline, an excessively long wordline pull-down time could result. PA1 1. There are fewer transistors to put on the wordline pitch. PA1 2. There are fewer interconnects since there are no RLB lines.
The second type of wordline driver is the strobed two-transistor wordline driver 200 shown in FIG. 2. The strobed two-transistor wordline driver is controlled by a strobe. An address transition detector (ATD) detects address changes and in response generates the STROBE signal. The STROBE terminates at the end of the cycle. The advantages of the strobed two-transistor wordline driver are:
The strobed two-transistor wordline driver suffers from a major disadvantage. The inherently large RC loading delay of the wordline results in a long selection and deselection time of the wordlines.
Hence a device and a method to more rapidly deselect an addressed wordline after a read or write operation has been completed is needed.